When data are sent over an extended high-speed serial link, a receiver at the receiving end of the link may be utilized to restore signal levels from the received signal, which may be attenuated by the link, and to re-synchronize the data with a local clock. The local clock may be formed from the data stream itself, transmitted on one or more data lanes as an embedded clock, or it may be formed from a forwarded clock transmitted on a separate clock lane. The local clock may or may not be a full rate clock, e.g., it may be a half-rate clock. The forwarded clock may have a frequency lower than that of the local clock. The selection of the scheme for transmitting a clock signal to the receiver, whether as an embedded clock or as a forwarded clock, is influenced by various factors such as the length of the link, the data rate to be utilized, or the number of available physical lanes. A designer designing multiple products may therefore require that two versions of a receiving circuit be available, one which is compatible with an embedded clock scheme and one which is compatible with a forwarded clock. This requirement is inconvenient and adds cost to supply and manufacturing operations, which may be required to stock two versions of otherwise similar or identical parts.
Thus, there is a need for a bimodal circuit capable of generating a local clock from either a forwarded clock or an embedded clock.